module counter_28(out,reset,clk);
input clk,reset;
output [5:0] out;
reg [5:0] out;
always @(posedge clk)
	begin
	if(reset) out<=0;
	else 
	out<=out+1;
	if(out==28) 
	  begin
	  for(out=28;out>0;out=out-1)
			begin
			end
	  end
	end
endmodule